Two types of well-known volatile semiconductor memories are dynamic random access memory (DRAM) and static random access memory (SRAM). A few of many differences between these memories are: (1) the DRAM cell is much smaller than the SRAM cell (e.g., by a factor of about 4 to 6 for the same technology), (2) a read operation in a DRAM is destructive (i.e., the cell data is lost), while a read operation in a SRAM is non-destructive, (3) due to leakage in DRAM cells, DRAMs require periodic refresh operations to maintain the stored data, while no refresh operation in required in SRAMs, and (4) read and write operations in a SRAM are faster than in a DRAM.
Because of the large SRAM cell size, the increase in SRAM density has been limited. Currently SRAMs with a storage capacity of greater than 16 Mb are being manufactured using 0.13 um technology. In contrast, because of the small size of the DRAM cell, the DRAM density has increased significantly with advancing technology. Currently DRAM having a storage capacity of 256 Mb or greater are being manufactured in 0.13 um technology.
In recent years, attempts have been made to eliminate the barrier to achieving high density SRAMs by using the DRAM cell in an SRAM device. To integrate the DRAM cell into an SRAM device, the refresh requirement of the DRAM cells needs to be properly addressed. In DRAM devices, a specific command is dedicated for refresh operations. Some SRAM vendors have changed the SRAM pin out to include a device pin for the refresh operations to enable integration of the DRAM cell into the SRAM device. However, because of the added refresh pin, these SRAM devices deviate from industry standard SRAM pin-outs, and thus can not be used as SRAM drop-in replacements.
Therefore, to be fully compatible with the SRAM industry standards, the refresh operation needs to be externally made transparent, i.e., be performed internally without any external control. Some SRAM vendors have produced such SRAM devices, however, these SRAM devices are slower than their conventional SRAM counterparts. The slow down is primarily due to the required refresh operations as described next with reference to FIGS. 1 and 2.
FIG. 1 shows a conventional shared bitline sense amplifier (BL_S/A) DRAM array architecture used in a SRAM device. Eight array sections Array_0 through Array_7 with a row of BL_S/A blocks between every two adjacent array sections is shown. Each BL_S/A block receives one pair of complimentary bitlines BL, {overscore (BL)} from the array section directly above it (i.e., “upper array”) and another pair of bitlines BL, {overscore (BL)} from the array section directly below it (i.e., the “lower block”), hence “the shared bitline sense amplifier array architecture”. This array architecture relaxes the BL_S/A pitch by a factor of 2 while reducing the die size since each BL_S/A block is shared by two pairs of bitlines. Thus, if each array section has 1024 pairs of BL, {overscore (BL)}, 512 BL_S/A blocks are needed between every two array sections.
Because of the shared BL_S/A configuration, in a read operation wherein a wordline is selected in one of the eight array sections, two rows of BL_S/A blocks directly above and below the array section with the selected wordline are activated. Upon completion of sensing, the two activated rows of BL_S/A are automatically precharged in preparation for the next operation.
A refresh operation is similar to a read operation, and is controlled by an on chip refresh address generator. Thus, a refresh cycle takes the same amount of time as a normal read cycle. Conventionally, refresh operations are embedded in between read operations. This results in a read access penalty as shown in FIG. 2.
FIG. 2A is a timing diagram showing two consecutive read cycles with a hidden refresh cycle in between. This timing diagram shows the worst case scenario wherein the selected wordline in each of the refresh cycle, the read cycle preceding the refresh cycles, and the read cycle succeeding the refresh cycle is within the same array section or within neighboring array sections.
As shown in FIG. 2A, a first read cycle corresponding to address Am is followed by a second read cycle corresponding to address An. In the first read cycle, wordline WLm is selected and automatically deselected upon completion of the sensing operation. This duration is indicated as tWL. Upon deselection of WLm, an automatic precharge operation occurs to precharge the two rows of activated BL_S/A blocks adjacent the array section in which the selected WLm is located. This precharge period is indicated as tPC. As shown, the wordline WLrefresh selected by the refresh address generator (not shown) cannot go high until precharge tPC is completed. This is because WLrefresh and WLm are within the same or neighboring array section, thus requiring the corresponding BL_S/A blocks to be fully precharged before wordline selection occurs.
Similar to the Am read cycle, the refresh cycle includes a wordline selection and sensing operation followed by a precharge operation tPC. The timing of the An read cycle is limited by the time at which precharge operation tPC ends. That is, WLn cannot go high until tPC is complete because, as indicated above, WLrefresh and WLn are within the same or neighboring arrays. Thus, it can be seen that a worst case read cycle tRC must accommodate two tWL periods and two tPC periods, as shown by the expression below:tRC(worst case)=2×(tWL+tPC)  (1)
The delay attributed to the refresh cycle would not cause a read access slow down if the WLfresh is in an array other than the same array or neighboring arrays of the array within which the selected WLn and WLm are located. However, because SRAMs are randomly accessed, the worst case speed path (tRC) constitutes the speed of the device.
FIG. 2B shows, in part, the timing relationship between the signals activating the sense amplifiers and the signal initiating a refresh cycle, as known in the prior art. Signals ras_act and SA_start respectively cause the array address and associated sense amplifiers to be activated. As seen from FIG. 2B, the time delay tPC is required to elapse between the initiation of signal refresh and the signal SA_done which represents the completion of the sensing operation. The read cycle tRC covers the time period between the assertion of signal ras_act and signal refresh.
Another issue that must be addressed if read cycles times similar to conventional SRAM devices are to be achieved, is the occurrence of invalid addresses. In conventional DRAM devices, invalid addresses do not cause a slow down in the memory operation because of the presence of the external clock. In conventional SRAMs, an invalid address does not cause a slow down because of the static nature of the memory. However, in SRAM devices with DRAM cells, invalid addresses can cause slow down in memory operation. In the absence of an external clock, any address change (valid or invalid) will propagate through the memory. Thus, if an invalid address occurs, and shortly thereafter a valid address occurs, the memory operation corresponding to the valid address needs to be delayed until the operation corresponding to the invalid address is completed.
Thus, a DRAM-based SRAM device fully compatible with standard SRAM pin-out, and device access time similar to high-speed SRAMs is desirable.